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Level Skip VLSI Architecture for 2D-Discrete Wavelet Transform

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Innovations in Computer Science and Engineering

Part of the book series: Lecture Notes in Networks and Systems ((LNNS,volume 8))

Abstract

A low power and efficient 2-D Discrete Wavelet Transform architecture is proposed. Previous DWT architectures utilized flipping structures or modified lifting based schemes. In this over-lapped strip based scanning is utilized to reduce the number of clock cycles for reading the input pixels. In addition that, second level prediction and updating equations are derived directly. It is observed that the number of adders and multipliers are reduced. The hardware utilization and power consumption is decreased in order to improve the performance of the discrete wavelet transform. The execution results expose that the suggested architecture is enhanced in area competence of 1% slices, 1% of DSP 48 s, multipliers and adders are also decreased.

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Correspondence to G. Kiran Maye .

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Kiran Maye, G., Srinivasulu, T. (2017). Level Skip VLSI Architecture for 2D-Discrete Wavelet Transform. In: Saini, H., Sayal, R., Rawat, S. (eds) Innovations in Computer Science and Engineering. Lecture Notes in Networks and Systems, vol 8. Springer, Singapore. https://doi.org/10.1007/978-981-10-3818-1_38

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  • DOI: https://doi.org/10.1007/978-981-10-3818-1_38

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  • Publisher Name: Springer, Singapore

  • Print ISBN: 978-981-10-3817-4

  • Online ISBN: 978-981-10-3818-1

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