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FPGA Based Low Power Hardware Implementation for Quality Access Control of a Compressed Gray Scale Image

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Computational Intelligence, Communications, and Business Analytics (CICBA 2017)

Part of the book series: Communications in Computer and Information Science ((CCIS,volume 775))

Abstract

This paper proposes a FPGA based hardware for quality access control of image based on passive data-hiding scheme in discrete cosine transform (DCT) domain. Host image is divided in to (8 × 8) non overlapping blocks and 2-D DCT is performed. The nonzero AC coefficients of a block are modulated based on modulation factor. The amount of quality degradation governs by modulation factor and interns perform quality access control. The modulated coefficients are Huffman coded for efficient storage and transmissions. All the necessary information are encoded and send to the decoder as a secret key along with the Huffman coded coefficient. User having the full knowledge of the key can demodulate to access full quality of image. Additionally, a low-power reliable hardware for real-time application is proposed and tested over large number of benchmark images. The experimental result shows its dominance in terms of optimized utilization of resource, very low power consumption of 71.735 mW and operates in a frequency of 113 MHz for processing of (256 × 256) sized images.

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Acknowledgements

The authors would like to thank the Ministry of Science and Technology (MOST), Taiwan R.O.C., under grant number MOST 106-3113-E-155-001-CC2, 105-3113-E-155-001, 104-3113-E-155-001, 103-3113-E-155-001, 103-2221-E-155-028-MY3 for their kind funding.

Author information

Authors and Affiliations

  1. Department of Photonics Engineering, Yuan Ze University, Taoyuan, Taiwan

    Himadri Mandal & Tien-Lung Chiu

  2. Department of Electronics and Communication Engineering, Netaji Subhash Engineering College, Garia, India

    Goutam Kr. Maity

  3. Department of Information Technology, MCKV Institute of Engineering, Liluah, India

    Amit Phadikar

Authors
  1. Himadri Mandal
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  2. Goutam Kr. Maity
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  3. Amit Phadikar
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  4. Tien-Lung Chiu
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Corresponding author

Correspondence to Himadri Mandal .

Editor information

Editors and Affiliations

  1. Department of Computer Science and Engineering, University of Kalyani, Kalyani, West Bengal, India

    J. K. Mandal

  2. Department of Computer and System Sciences, Visva Bharati University, Bolpur Santiniketan, West Bengal, India

    Paramartha Dutta

  3. Department of Information Technology, Calcutta Business School, Kolkata, India

    Somnath Mukhopadhyay

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Mandal, H., Maity, G.K., Phadikar, A., Chiu, TL. (2017). FPGA Based Low Power Hardware Implementation for Quality Access Control of a Compressed Gray Scale Image. In: Mandal, J., Dutta, P., Mukhopadhyay, S. (eds) Computational Intelligence, Communications, and Business Analytics. CICBA 2017. Communications in Computer and Information Science, vol 775. Springer, Singapore. https://doi.org/10.1007/978-981-10-6427-2_34

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  • DOI: https://doi.org/10.1007/978-981-10-6427-2_34

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  • Publisher Name: Springer, Singapore

  • Print ISBN: 978-981-10-6426-5

  • Online ISBN: 978-981-10-6427-2

  • eBook Packages: Computer ScienceComputer Science (R0)

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