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FOWLP: PoP

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Fan-Out Wafer-Level Packaging

Abstract

Package-on-package (PoP) has been used for housing the application processor (AP) chipset for a few years as shown in Fig. 2.17. Usually, the top package is used to house the mobile memory and the bottom package is used to house the AP. STATS ChipPAC proposed a PoP for the AP chipset with the FOWLP technology (Eslampour et al in IEEE/ECTC proceedings, 1946–1950, [1]; Yoon et al. in Proceedings of IEEE/ECTC, 1250–1254, [2]).

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References

  1. Eslampour, H., S. Lee, S. Park, T. Lee, I. Yoon, and Y. Kim. 2010. Comparison of Advanced PoP Package Configurations. In IEEE/ECTC Proceedings, 2010, 1946–1950.

    Google Scholar 

  2. Yoon, S., J. Caparas, Y. Lin, and P. Marimuthu. 2012. Advanced Low Profile PoP Solution with Embedded Wafer Level PoP (eWLB-PoP) Technology. In Proceedings of IEEE/ECTC, 2012, 1250–1254.

    Google Scholar 

  3. Lin, J.C., J.P. Hung, N.W. Liu, Y.C. Mao, W.T. Shih, and T.H. Tung. 2015. Packaged Semiconductor Device with a Molding Compound and a Method of Forming the Same. US Patent 9,000,584, Filed on December 28, 2011, Patented on April 7, 2015.

    Google Scholar 

  4. Liu, C., S. Chen, F. Kuo, H. Chen, E. Yeh, C. Hsieh, L. Huang, M. Chiu, J. Yeh, T. Lin, T. Yeh, S. Hou, J. Hung, J. Lin, C. Jou, C. Wang, S. Jeng, and D. Yu. 2012. High-Performance Integrated Fan-Out Wafer Level Packaging (InFO-WLP): Technology and System Integration. In IEEE/IEDM Proceedings, 2012, 14.1.1–14.1.4.

    Google Scholar 

  5. Tsai, C., J. Hsieh, M. Liu, E. Yeh, H. Chen, C. Hsiao, C. Chen, C. Liu, M. Lii, C. Wang, and D. Yu. 2013. Array Antenna Integrated Fan-out Wafer Level Packaging (InFO-WLP) for Millimeter Wave System Applications. In IEEE/IEDM Proceedings, 2013, 25.1.1–25.1.4.

    Google Scholar 

  6. Chen, S.M., L.H. Huang, J.H. Yeh, Y.J. Lin, F.W. Kuo, H.N. Chen, M.Y. Chiu, C.C. Liu, J. Yeh, T.J. Yeh, S.Y. Hou, J.P. Hung, J.C. Lin, C.P. Jou, S.P. Jeng, and D. Yu. 2013. High-Performance Inductors for Integrated Fan-Out Wafer Level Packaging (InFO-WLP). In Symposium on VLSI Technology Digest of Technical Papers, 2013, T46–T47.

    Google Scholar 

  7. Yu, D. 2014. Wafer-Level System Integration (WLSI) Technologies for 2D and 3D System-in-Package. In SEMIEUROPE, 2014.

    Google Scholar 

  8. Yu, D. 2015. New Integration Technology Platform: Integrated Fan-Out Wafer-Level-Packaging for Mobile Applications. In Symposium on VLSI Technology Digest of Technical Papers, 2015, T46–T47.

    Google Scholar 

  9. Tseng, C., C. Liu, C. Wu, and D. Yu. 2016. InFO (Wafer Level Integrated Fan-Out) Technology. In IEEE/ECTC Proceedings, 2016, 1–6.

    Google Scholar 

  10. Hsieh, C., C. Wu, and D. Yu. 2016. Analysis and Comparison of Thermal Performance of Advanced Packaging Technologies for State-of-the-Art Mobile Applications. In IEEE/ECTC Proceedings, 2016, 1430–1438.

    Google Scholar 

  11. Lau, J.H., N. Fan, M. Li. 2016. Design, Material, Process, and Equipment of Embedded Fan-Out Wafer/Panel-Level Packaging. Chip Scale Review 20: 38–44.

    Google Scholar 

  12. Lau, J.H., M. Li, D. Tian, N. Fan, E. Kuah, K. Wu, et al. 2017. Warpage and Thermal Characterization of Fan-Out Wafer-Level Packaging. In IEEE/ECTC Proceedings, 2017, 595–602. Also, IEEE Transactions on CPMT 7 (10), 1729–1938 (October 2017).

    Google Scholar 

  13. Lau, J.H., M. Li, N. Fan, E. Kuah, Z. Li, K. Tan, T. Chen, et al. 2017. Fan-Out Wafer-Level Packaging (FOWLP) of Large Chip With Multiple Redistribution-Layers (RDLs). In IMAPS Proceedings, October 2017, 576–583. Also, IMAPS Transactions, Journal of Microelectronics and Electronic Packaging 14 (4), 123–131 (October 2017).

    Google Scholar 

  14. Li, M., Q. Li, J.H. Lau, N. Fan, E. Kuah, K. Wu, et al. 2017. Characterizations of Fan-Out Wafer-Level Packaging. In IMAPS Proceedings, October 2017, 557–562.

    Google Scholar 

  15. Hua, X., H. Xu, Z. Li Zhang, D. Chen, K. Tan, J.H. Lau, et al. 2017. Development of Chip-First and Die-Up Fan-Out Wafer-Level Packaging. In IEEE/EPTC Proceedings, December 2017, S23_1-6.

    Google Scholar 

  16. Lau, J.H. 2015. Patent Issues of Fan-Out Wafer/Panel-Level Packaging. Chip Scale Review 19: 42–46.

    Google Scholar 

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Lau, J.H. (2018). FOWLP: PoP. In: Fan-Out Wafer-Level Packaging. Springer, Singapore. https://doi.org/10.1007/978-981-10-8884-1_8

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  • DOI: https://doi.org/10.1007/978-981-10-8884-1_8

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