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FPGA Realization of Scale-Free CORDIC Algorithm-Based Window Functions

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Recent Trends in Communication, Computing, and Electronics

Part of the book series: Lecture Notes in Electrical Engineering ((LNEE,volume 524))

Abstract

Filtering is an immense process in spectral analysis of signals. In designing of filters, window functions are usually used. In this paper, we present the variety of window functions based on the scale-free COordinate Rotation DIgital Computer (CORDIC) algorithm for the target angle which covers the complete coordinate space. To overcome the problem of more occupied area and speed, we present a study of a different design that is scale-free CORDIC algorithm-based window function architectures. The current paper presents the simulation and synthesis results of two designs which are coded in very high speed integrated circuit hardware description language (VHDL). The Xilinx 13.1 software is used for the simulation and synthesis of coded design, and also these designs are mapped into Virtex-5(XC5VLX20T-FF323) field-programmable gate array (FPGA) device.

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References

  1. Parhi, K. K. (1999). VLSI digital signal processing systems. Wiley.

    Google Scholar 

  2. Ray, K. C., & Dhar, A. S. (2006). CORDIC–based unified VLSI architecture for implementing window functions for real time spectral analysis. IEEE Proceedings: Circuits, Devices and Systems, 153(6), 539–544.

    Google Scholar 

  3. Ray, K. C., & Dhar, A. S. (2008). High throughput VLSI architecture for Blackman windowing in real spectral analysis. Journal of Computers, 3(5), 54–59.

    Article  Google Scholar 

  4. Vaidyanathan, P. P. (1985). A unified approach to orthogonal digital filters and wave digital filters based on the LBR two- pair extraction. IEEE Transactions on Circuits and Systems I, CAS-32, 673–686.

    Article  Google Scholar 

  5. Banerjee, A., Dhar, A. S., & Banerjee, S. (2001). FPGA realization of a CORDIC based FFT processor for biomedical signal processing. Microprocessors and Micro System, 25(3), 131–142.

    Article  Google Scholar 

  6. Gisuthan, B., & Srikanthan, T. (2000). FLAT CORDIC: A unified architecture for high speed generation of trigonometric and hyperbolic functions. In Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems, Lansing MI (pp. 1414–1417).

    Google Scholar 

  7. Juang, T. B., Hsiao, S. F., & Tsai, M. Y. (2004). Para-CORDIC: Parallel CORDIC rotation algorithm. IEEE Transactions on Circuits and Systems I, 51(8), 1515–1524.

    Article  MathSciNet  Google Scholar 

  8. Lin, C. H., & Wu, A. Y. (2005). Mixed-scaling-rotation-CORDIC (MSR-CORDIC) algorithm and architecture for high-performance vector rotational DSP applications. IEEE Transactions on Circuits and Systems I, 52(11), 2385–2396.

    Article  Google Scholar 

  9. Sumanasen, M. G. B. (2008). A scale factor correction scheme for the CORDIC algorithm. IEEE Transactions on Computers, 57(8), 1148–1152.

    Article  MathSciNet  Google Scholar 

  10. Maharatna, K., Troya, A., Banerjee, S., & Grass, E. (2004). Virtually scaling free adaptive CORDIC rotator. IEEE Proceedings Computers and Digital Techniques, 151(6), 448–456.

    Article  Google Scholar 

  11. Maharatna, K., & Banerjee, S. (2005). Modified virtually scaling free adaptive CORDIC rotator algorithm and architecture. IEEE Transactions on Circuits and Systems for Video Technology, 15(11), 1463–1474.

    Article  Google Scholar 

  12. Jaime, F. J., Sanchez, M. A., Hormigo, J., Villalba, J., & Zapata, E. L. (2010). Enhanced scaling free CORDIC. IEEE Transactions on Circuits and Systems Video Technology, 57(7), 1654–1662.

    MathSciNet  Google Scholar 

  13. Volder, J. E. (1959). The CORDIC trigonometric Computing technique. IRE Transactions on Electronic Computers, 8(3), 330–334.

    Article  Google Scholar 

  14. Volder, J. E. (2000). The birth of CORDIC. Journal of VLSI Signal Processing, 25(2), 101–105.

    Article  Google Scholar 

  15. Walther, J. S. (1971). A unified algorithm for elementary functions. In Proceedings of AFIPS Spring Joint Computer Conference (pp. 379–385).

    Google Scholar 

  16. Walther, J. S. (2000). The story of unified CORDIC. Journal of VLSI Signal Processing, 25(2), 107–112.

    Article  MathSciNet  Google Scholar 

  17. Meher, P. K., Valls, J., Juang, T. B., Sridhara, K., & Maharatna, K. (2009). 50 years of CORDIC algorithms, architectures and applications. IEEE Transactions Circuits and Systems I, 56(9), 1893–1907.

    Article  MathSciNet  Google Scholar 

  18. Aggarwal, S., Khare. K. (2012). Redesigned-scale-free CORDIC algorithm based FPGA implementation of window functions to minimize area and latency. International Journal of Reconfigurable Computing, 2012(185784), 1–8.

    Article  Google Scholar 

  19. Aggarwal, S., Meher, P. K., & Khare, K. (2013). Scale-free hyperbolic CORDIC processor and its application to waveform generation. IEEE Transactions on Circuits and System-I Regular Papers, 60(2), 314–326.

    Article  MathSciNet  Google Scholar 

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Author information

Authors and Affiliations

  1. Department of Electronics and Communication, University of Allahabad, Allahabad, India

    Shalini Rai & Rajeev Srivastava

Authors
  1. Shalini Rai
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  2. Rajeev Srivastava
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Corresponding author

Correspondence to Rajeev Srivastava .

Editor information

Editors and Affiliations

  1. University of Allahabad, Allahabad, India

    Ashish Khare

  2. Indian Institute of Information Technology, Allahabad, Uttar Pradesh, India

    Uma Shankar Tiwary

  3. Oakland University, Rochester, MI, USA

    Ishwar K. Sethi

  4. University of Allahabad, Allahabad, Uttar Pradesh, India

    Nar Singh

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Rai, S., Srivastava, R. (2019). FPGA Realization of Scale-Free CORDIC Algorithm-Based Window Functions. In: Khare, A., Tiwary, U., Sethi, I., Singh, N. (eds) Recent Trends in Communication, Computing, and Electronics. Lecture Notes in Electrical Engineering, vol 524. Springer, Singapore. https://doi.org/10.1007/978-981-13-2685-1_24

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  • DOI: https://doi.org/10.1007/978-981-13-2685-1_24

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  • Publisher Name: Springer, Singapore

  • Print ISBN: 978-981-13-2684-4

  • Online ISBN: 978-981-13-2685-1

  • eBook Packages: EngineeringEngineering (R0)

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