Abstract
This work shows importance of reversible logic circuits using One-Hot Residue Number System (OHRNS) for arithmetic circuit designing and signal processing (digital) for less delay and less power dissipation applications. OHRNS technique highlight is delay of one active (high) transistor which is equal to the implementation delay which shows better results in comparison to reversible logic design circuits and conventional methods. Another benefit of using OHR is lucidity of implementation when compared to reversible logic circuits and conventional methods. The advantage of using reversible logic design circuits is having minimal power dissipation. Design of arithmetic blocks adder and subtractor using one-hot encoding technique is focused mainly. Frequently these subsystems are used in the design of filters. In this work, the above subsystems implemented using OHR are utilized in designing of FFT computational blocks. The essential blocks required in designing a fast Fourier transform computation block using conventional, OHRNS, reversible logic circuits methods, are implemented in Tanner EDA tool with standard CMOS technology (250 nm), and comparative results are provided. Experimental results show the FFT block implementation using OHRNS technique which dissipates less power, consumes less transistors, and is faster and feasible option in design of efficient circuits when compared to similar implementation techniques such as reversible logic circuits and conventional techniques.
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We would like to thank the department of ECE, PES University for the tool support.
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Appendix
Appendix
1.1 Reversible Logic Design Modulo-5 One-Hot Adder
The illustration of modulo-5 addition using RLD with an example is shown in Table 8. The processing of data input vector with respect to shift input happens due to barrel shifting action.
Taking an example,
Data input (Input-1) = 01000 (represents 3 in decimal).
Shift input (Input-2) = 00010 (represents 1 in decimal).
Modulo-5 addition of both inputs results in output 10000 (4 in decimal).
Operation of modulo-5 adder with different combinations of inputs is listed in Table 9. In Fig. 14, OHRNS mod-5 adder simulation waveform is shown with inputs listed in Table 9.
Waveform of modulo-5 adder reversible logic design
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Jaswanth Vuggirala, Patil, G.N., Jayashree, H.V. (2019). Design and Functional Verification of Reversible Logic Based FFT Using OHRNS. In: Nath, V., Mandal, J. (eds) Proceedings of the Third International Conference on Microelectronics, Computing and Communication Systems. Lecture Notes in Electrical Engineering, vol 556. Springer, Singapore. https://doi.org/10.1007/978-981-13-7091-5_32
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DOI: https://doi.org/10.1007/978-981-13-7091-5_32
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