Abstract
Reversible logic offers an alternative computation for future low-power computing devices. In this paper, an efficient and potent universal 33 and 44 reversible gates are considered to implement 4-bit counter. Performance of the proposed 33 gate is verified using thirteen standard three variables Boolean functions, which demonstrate from 17.8 to 45.2% superiority in term of gate counts obtained with other reversible gates. New structures for T flip-flop and D flip-flop, which utilize two efficient reversible gates are presented. These flip-flops and some existing gates are utilized to implement the Mod-16 counter and 4-bit Up/down counter. The reported architectures are modeled using VHDL and functional simulations are done using ISIM.
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Sasamal, T.N., Gaur, H.M., Singh, A.K., Mohan, A. (2020). Novel Approaches for Designing Reversible Counters. In: Singh, A., Fujita, M., Mohan, A. (eds) Design and Testing of Reversible Logic. Lecture Notes in Electrical Engineering, vol 577. Springer, Singapore. https://doi.org/10.1007/978-981-13-8821-7_3
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DOI: https://doi.org/10.1007/978-981-13-8821-7_3
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