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Basic Analysis of Single-Input Single-Output (SISO) PCB Interconnect Structure

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Analytical Methodology of Tree Microstrip Interconnects Modelling For Signal Distribution
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Abstract

The last century was particularly remarkable with the spectacular progress of the microelectronic semiconductor industries. This constant technological progress was till now unique in the mankind history. It is nowadays a source of innovative product developments in numerous civil sectors as the mobile phones, multimedia systems, medical equipments and even vehicles.

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References

  1. International Technology Roadmap for Semiconductors Update Overview, [Online] http://www.itrs.net/Links/2016ITRS/Home2016.htm

  2. A. Deutsch, High-speed signal propagation on lossy transmission lines. IBM J. Res. Develop. 34(4), 601–615 (1990)

    Article  MathSciNet  Google Scholar 

  3. M. Celik, L. Pileggi, A. Odabasioglu, IC Interconnect Analysis (Kluwer Academic Publisher, Dordrecht, 2002), 1-4020-7075-6

    Google Scholar 

  4. A. Ligocka-Wardzińska, W. Bandurski, Sensitivity of output response to geometrical dimensions in VLSI interconnects. in Proceedings of 13th IEEE Workshop SPI (Strasbourg, France, May 2009), pp. 1–4

    Google Scholar 

  5. C.-N. Chiu, I.-T. Chiang, A fast approach for simulating long-time response of high-speed dispersive and lossy interconnects terminated with nonlinear loads. Prog. Electromagnet. Res. PIER 91, 153–171 (2009)

    Article  Google Scholar 

  6. M. Ghoneima, Y. Ismail, M.M. Khellah, J. Tschanz, V. De, Serial-link bus: A low-power on-chip bus architecture. IEEE Trans. CAS I 56(9), 2020–2032 (2009)

    MathSciNet  Google Scholar 

  7. M.-E. Hwang, S.-O. Jung, K. Roy, Slope interconnect effort: Gate-interconnect interdependent delay modeling for early CMOS circuit simulation. IEEE Trans. CAS I 56(7), 1428–1441 (2009)

    MathSciNet  Google Scholar 

  8. W.C. Elmore, The transient response of damped linear networks. J. Appl. Phys. 19, 55–63 (1948)

    Article  Google Scholar 

  9. J.L. Wyatt, Circuit Analysis, Simulation and Design (Elsiever Science, North-Holland, The Netherlands, 1978)

    Google Scholar 

  10. A.B. Kahng, S. Muddu, An analytical delay model of RLC interconnects. IEEE Trans. Comput.-Aided Des. 16, 1507–1514 (1997)

    Article  Google Scholar 

  11. Y.I. Ismail, E.G. Friedman, Effects of inductance on the propagation, delay and repeater insertion in VLSI circuits. IEEE Trans. VLSI Sys. 8(2), 195–206 (2000)

    Article  Google Scholar 

  12. Y.I. Ismail, E.G. Friedman, J.L. Neves, Equivalent Elmore delay for RLC trees. IEEE Trans. CAD 19(1), 83–97 (2000)

    Article  Google Scholar 

  13. A. Ligocka, W. Bandurski, Effect of inductance on interconnect propagation delay in VLSI circuits. in Proceedings of 8th IEEE Workshop SPI, (9–12 May 2004), pp. 121–124

    Google Scholar 

  14. P.A.W. Basl, M.H. Bakr, N.K. Nikolova, Efficient transmission line modeling sensitivity analysis exploiting rubber cells. Prog. Electromagnet. Res. PIER B 11, 223–243 (2009)

    Article  Google Scholar 

  15. H. Xie, J. Wang, R. Fan, Y. Liu, Study of loss effect of transmission lines and validity of a Spice model in electromagnetic topology. Prog. Electromagnet. Res. PIER 90, 89–103 (2009)

    Article  Google Scholar 

  16. E.O. Hammerstad, O. Jensen, Accurate models for microstrip computer aided design. IEEE Trans. MTT. 407–409 (1980)

    Google Scholar 

  17. E.O. Hammerstad, Equations for microstrip circuit design. in Proceedings of 5th EuMC (Hamburg, Germany, 1–4 September 1975), pp. 268–272

    Google Scholar 

  18. R.B. Marks, D.F. Williams, Interconnection transmission line parameter characterization. in Proceedings of 40th ARTG Conference on Digest (Orlando, FL, USA, December 1992), pp. 88–95

    Google Scholar 

  19. R.B. Marks, D.F. Williams, Characteristic impedance determination using propagation constant measurement. IEEE Microwave Guided Wave Lett. 1(6), 141–143 (1991)

    Article  Google Scholar 

  20. W.R. Eisenstadt, Y. Eo, S-parameter-based IC interconnect transmission line characterization. IEEE Trans. Comp. Hybrids Manuf. Technol. 15(4), 483–490 (1992)

    Article  Google Scholar 

  21. A. Deutsch, R.S. Krabbenhoft, K.L. Melde, C.W. Surovic, G.A. Katopis, G.V. Kopcsay, Z. Zhou, Z. Chen, Y.H. Kwark, T.-M. Winkel, X. Gu, T.E. Standaert, Application of the short-pulse propagation technique for broadband characterization of PCB and other interconnect technologies. IEEE Trans. EMC 52(2) 266–287 (February 2010)

    Article  Google Scholar 

  22. J. Cong, L. He, C.-K. Koh, P. Madden, Performance optimization of VLSI interconnect. Integration VLSI J. 21(1–2), 1–94 (1996)

    Article  Google Scholar 

  23. B. Yun, S.S. Wong, Optimization of driver preemphasis for on-chip interconnects. IEEE Trans. CAS I 56(9), 2033–2041 (2009)

    MathSciNet  Google Scholar 

  24. J. Rosenfeld, E.G. Friedman, Design methodology for global resonant H-tree clock distribution networks. IEEE Trans. VLSI Systems 15(2), 135–148 (2007)

    Article  Google Scholar 

  25. F.R. Awwad, M. Nekili, V. Ramachandran, M. Sawan, On modeling of parallel repeater-insertion methodologies for SoC interconnects. IEEE Trans. CAS I 55(1), 322–335 (2008)

    MathSciNet  Google Scholar 

  26. B. Ravelo, A. Perennec, M. Le Roy, Experimental validation of the RC-interconnect effect equalization with negative group delay active circuit in planar hybrid technology. in Proceedings of 13th IEEE Workshop SPI (Strasbourg, France, 12–15 May 2009), pp. 1–4

    Google Scholar 

  27. B. Ravelo, A. Perennec, M. Le Roy, New technique of inter-chip interconnect effects equalization with negative group delay active circuits. in VLSI, Chap. 20, ed. Z. Wang (INTECH, February 2010), pp. 409–434

    Google Scholar 

  28. J. Zhang, T.Y. Hsiang, Extraction of subterahertz transmission-line parameters of coplanar waveguides. Prog. Electromagnet. Res. PIERS 3(7), 1102–1106 (2007)

    Google Scholar 

  29. C.V. Kashyap, C.J. Alpert, F. Liu, A. Devgan, Closed-form expressions for extending step delay and slew metrics to ramp inputs for RC trees. IEEE Trans. CADICAS I 23(4), 509–516 (2004)

    Article  Google Scholar 

  30. B. Ravelo, L. Rajaoarisoa, Numerical modeling of high-speed microelectronic interconnects for the signal integrity analysis. Int. J. Emerg. Sci. 3(1), 1–14 (2013)

    Google Scholar 

  31. R.A. Pucel, D.J. Massé, C. Hartwing, Losses in microstrip. IEEE Trans. MTT 16(6), 342–350 (1968)

    Article  Google Scholar 

  32. M. Kirschning, R.H. Jansen, Accurate model for effective dielectric constant with validity up to millimeter-wave frequencies. Electron. Lett. 18, 272–273 (1982)

    Article  Google Scholar 

  33. D M. Pozar, Microwave Engineering, 2nd edn. (Wiley, 1988), pp. 9–21, 154–166

    Google Scholar 

  34. C. Chen, J. Lillis, S. Lin, N. Chang, Interconnect analysis and synthesis (Wiley, New York, 2000)

    Google Scholar 

  35. T. Eudes, B. Ravelo, A. Louis, Experimental validations of a simple PCB interconnect model for high-rate signal integrity. IEEE Tran. EMC 54(2), 397–404 (2012)

    Google Scholar 

  36. L.P. Carloni, A.B. Kahng, S.V. Muddu, A. Pinto, K. Samadi, P. Sharma, Accurate predictive interconnect modeling for system-level design. IEEE Tran. VLSI 18(4), 679–684 (2010)

    Article  Google Scholar 

  37. T. Eudes, B. Ravelo, A. Louis, Transient response characterization of the high-speed interconnection RLCG-model for the signal integrity analysis. Prog. Electromagnet. Res. 112, 183–197 (2011)

    Article  Google Scholar 

  38. G.H. Zhang, M.Y. Xia, X.M. Jiang, Transient analysis of wire structures using time domain integral equation method with exact matrix elements. Prog. Electromagnet. Res. PIER 92, 281–298 (2009)

    Article  Google Scholar 

  39. Agilent EEsof EDA, Overview: Electromagnetic Design System (EMDS) (September 2008) [Online]. Available: http://www.agilent.com/find/eesof-emds

  40. Ansoft corporation, Simulation Software: High-performance Signal and Power Integrity. Internal Report (2006)

    Google Scholar 

  41. ANSYS, Unparalleled Advancements in Signal- and Power-Integrity, Electromagnetic Compatibility Testing (16 June 2009), [Online]. Available: http://investors.ansys.com/

  42. North East Systems Associates (NESA), RJ45 Interconnect Signal Integrity (CST Computer Simulation Technology AG, 2010), [Online]. Available: http://www.cst.com/Content/Applications/Article/Article.aspx?id=243

  43. B. Ravelo, T. Eudes, A.K. Jastrzebski, Investigation of Reduced Models of Capacitive Loaded Interconnects for the High-Speed SI Applications. in Proceedings of 10th International Symposium on Electromagnetic Compatibility (EMC) Europe 2011 (York, UK, 26–30 September 2011), pp. 357–361

    Google Scholar 

  44. 240-Pin PC-6400/PC-5300/PC-4200/PC-3200 DDR2 SDRAM Registered DIMM Design Specification. JEDEC Standard, No. 21C, Rev. 4.04, Januay 2010. [Online]. Available: http://www.jedec.org

  45. S. Lin, E.S. Kuh, Transient simulation of lossy interconnects based on the recursive convolution formulation. IEEE Trans. CAS 39(11), 879–892 (1992)

    Article  Google Scholar 

  46. X.C. Li, J.F. Mao, M. Swaminathan, Transient analsysis of C-MOS gate driven RLCG interconnects based on FDTD. IEEE Trans. CADICS 30(4), 574–583 (2011)

    Article  Google Scholar 

  47. C.N. Chiu, I.T. Chiang, A fast approach for simulating long-time response of high-speed dispersive and lossy interconnects terminated with nonlinear loads. Prog. Electromagnet. Res. (PIER) 91, 153–171 (2009)

    Article  Google Scholar 

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Correspondence to Blaise Ravelo .

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Eudes, T., Ravelo, B. (2020). Basic Analysis of Single-Input Single-Output (SISO) PCB Interconnect Structure. In: Ravelo, B. (eds) Analytical Methodology of Tree Microstrip Interconnects Modelling For Signal Distribution. Springer, Singapore. https://doi.org/10.1007/978-981-15-0552-2_2

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  • DOI: https://doi.org/10.1007/978-981-15-0552-2_2

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