Performance Analysis of Data Communication Using Hybrid NoC for Low Latency and High Throughput on FPGA

Abstract

The perception of the theory of communication network has led to enormous supplanting committed to simplex, duplex system in terms of various scales of interconnecting systems and switches. Each data interactive system needs to have a smart way for the design of efficient and tolerant system in terms of adaptability, versatility, execution, and effective data delivery. In this peculiarity, the system architects demand for a novel network on-chip router which is error free and minimized circuit path with greater packet delivery ratio, minimum delay, and better bandwidth utilization. In this paper, we propose the modeling of network architecture in consideration with 8 × 8 switch router which indulges the suitable algorithm for shortest path finder, i.e., minimum spanning tree, for efficient routing in run-time. We have demonstrated warmhole technique and virtual cut-through mechanisms for automatic correction with validating errors. So, we have selected verilog HDL for development under the environment of VIVADO Xilinx 2018-1 and demonstrated on Nexys DDR-4 Artix-7 Field Programmable Gate Array family bearing part number XCA7CGS100t comprised of 324 pins with the results it is noticed that better reliability and minimized latency of 36.5% with enhanced throughput reaching 40% than the existing router. The proposed design is acceptable in terms of better performance in terms of area, delay, and resource allocation.