Design of Super-Pipeline Architecture to Visualize the Effect of Dependency

Abstract

Nowadays, pipelining is a very common phenomenon for getting speedup in processors. Super-pipeline architecture can issue more than one instruction in less than one clock cycle but dependency is major obstacle in super-pipeline architecture because dependency puts a stop in issuing the instruction in less than one clock cycle. In this paper, a simulator is designed for visualizing the effect of dependency on super-pipeline architecture. With the help of a simulator, we can make any previous instructions and instruction can be dependent on current instruction (dependency can be of any type like it can be of data dependency or control dependency or resource conflicts). Simulator also visualizes the effect of dependency for each instruction like how many numbers of stalls are encountered to handle dependency, in which cycle stall is encountered, how many clock cycles required to execute the instruction, and then finally, simulator calculates the performance parameters like total clock cycles, stalls, CPI, IPC, and speedup.